Let's build a processor !

We finally choose Zscale (by Berkeley Architecture Research) as the core for our project as it had a verilog implementation and was a simplistic core using RISC-V ISA, meeting all our specifications.

The Zscale core like any other processor consisted of the standard modules found in a processor :

• Controller 
• ALU (Arithmetic and Logic Unit) 
• Register File 
• CSR File 
• Pipeline stages
• Immediate Generators
• Muxes

Currently we have ported all the modules to myHDL with tests (with the exception of one module) and we are currently assembling them to form the core. 

Zscale is just like another processor implementation, the reason why such a complex processor can be described in hardware so compactly is because of the beautifully designed ISA. 

As I was converting the core to myHDL, I realised the placement of each every bit in the ISA was a ingeniously planned thought which made it easy to write logic for the processor. 

To conclude, as we near the completion of this processor, the entire myHDL community will have a  RISCV processor which supports the RV32I ( crux of the ISA ).

See you next week,

MS 

RISC-V Core review

The last two weeks have mostly been debugging and reviewing cores for our project. I had gathered all riscv implementations and then I reviewed them this week. Here is a list of the cores I reviewed.

I also was struggling with my health last week and thus could not post on the blog. I am also working on the decoder debugging currently as a side task.

Core Review

Cores :

• Yarvi
• Zscale
• Shakti
• E Class
• C Class
• PicoRV32

Yarvi

• Type : In-order , 3 stage pipeline
• Source : SystemVerilog
• ISA : RV32I
• Cache : None
• Branch Predictor : None
• Instruction Mem : 4KB
• Data Mem : 4KB
• Memory Interface : Avalon-MM
• RISCV toolchain : riscv32-unknown-elf-gcc
• Simulation support : Yes
• In development : No
• Future updates : No

Zscale

• Source : Chisel and Verilog (vscale)
• Type : Single-issue, In-order , 3 stage pipeline
• ISA : RV32
• Cache : None
• Branch Predictor : None
• Instruction Mem : 4KB
• Data Mem : 4KB
• Memory Interface : AHB-Lite bus
• In development : Yes
• Future updates : Yes
• RISCV toolchain : riscv32
• Simulation support : Yes

SHAKTI Cores

E Class

• Source : Bluespec
• Type : In-order , 3 stage pipeline
• ISA : RV32I
• Cache : L2
• Branch Predictor : Custom
• Instruction Mem : 4KB
• Data Mem : 4KB
• Memory Interface : AXI
• In development : Yes
• Future updates : Yes
• RISCV toolchain : riscv32
• Simulation support : No

C Class

• Source : Bluespec
• Type : In-order , 8 stage pipeline
• ISA : RV32I
• Cache : L2
• Branch Predictor : Custom
• Instruction Mem : 4KB
• Data Mem : 4KB
• Memory Interface : AXI
• In development : Yes
• Future updates : Yes
• RISCV toolchain : None
• Simulation support : No

PicoRV32

• Source : Verilog
• Type : In-order , 8 stage pipeline
• ISA : RV32IMC
• Cache : L2
• Branch Predictor : Custom
• Instruction Mem : 4KB
• Data Mem : 4KB
• Memory Interface : AXI Lite
• In development : Yes
• Future updates : Yes
• RISCV toolchain : rv32
• Simulation support : No

See you until next week !

MS.