We finally choose Zscale (by Berkeley Architecture Research) as the core for our project as it had a verilog implementation and was a simplistic core using RISC-V ISA, meeting all our specifications.
The Zscale core like any other processor consisted of the standard modules found in a processor :
The Zscale core like any other processor consisted of the standard modules found in a processor :
- Controller
- ALU (Arithmetic and Logic Unit)
- Register File
- CSR File
- Pipeline stages
- Immediate Generators
- Muxes
Currently we have ported all the modules to myHDL with tests (with the exception of one module) and we are currently assembling them to form the core.
Zscale is just like another processor implementation, the reason why such a complex processor can be described in hardware so compactly is because of the beautifully designed ISA.
As I was converting the core to myHDL, I realised the placement of each every bit in the ISA was a ingeniously planned thought which made it easy to write logic for the processor.
To conclude, as we near the completion of this processor, the entire myHDL community will have a RISCV processor which supports the RV32I ( crux of the ISA ).
See you next week,
MS
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