The last two weeks have mostly been debugging and reviewing cores for our project. I had gathered all riscv implementations and then I reviewed them this week. Here is a list of the cores I reviewed.
I also was struggling with my health last week and thus could not post on the blog. I am also working on the decoder debugging currently as a side task.
I also was struggling with my health last week and thus could not post on the blog. I am also working on the decoder debugging currently as a side task.
Core Review
Cores :
- Yarvi
- Zscale
- Shakti
- E Class
- C Class
- PicoRV32
Yarvi
- Type : In-order , 3 stage pipeline
- Source : SystemVerilog
- ISA : RV32I
- Cache : None
- Branch Predictor : None
- Instruction Mem : 4KB
- Data Mem : 4KB
- Memory Interface : Avalon-MM
- RISCV toolchain : riscv32-unknown-elf-gcc
- Simulation support : Yes
- In development : No
- Future updates : No
Zscale
- Source : Chisel and Verilog (vscale)
- Type : Single-issue, In-order , 3 stage pipeline
- ISA : RV32
- Cache : None
- Branch Predictor : None
- Instruction Mem : 4KB
- Data Mem : 4KB
- Memory Interface : AHB-Lite bus
- In development : Yes
- Future updates : Yes
- RISCV toolchain : riscv32
- Simulation support : Yes
SHAKTI Cores
E Class
- Source : Bluespec
- Type : In-order , 3 stage pipeline
- ISA : RV32I
- Cache : L2
- Branch Predictor : Custom
- Instruction Mem : 4KB
- Data Mem : 4KB
- Memory Interface : AXI
- In development : Yes
- Future updates : Yes
- RISCV toolchain : riscv32
- Simulation support : No
C Class
- Source : Bluespec
- Type : In-order , 8 stage pipeline
- ISA : RV32I
- Cache : L2
- Branch Predictor : Custom
- Instruction Mem : 4KB
- Data Mem : 4KB
- Memory Interface : AXI
- In development : Yes
- Future updates : Yes
- RISCV toolchain : None
- Simulation support : No
PicoRV32
- Source : Verilog
- Type : In-order , 8 stage pipeline
- ISA : RV32IMC
- Cache : L2
- Branch Predictor : Custom
- Instruction Mem : 4KB
- Data Mem : 4KB
- Memory Interface : AXI Lite
- In development : Yes
- Future updates : Yes
- RISCV toolchain : rv32
- Simulation support : No
See you until next week !
MS.
Too much time has been spent on reviewing these cores, at this point in time just pick one. I do not want to see another update that simply indicates reviewing the cores. There should be significant code contributions in the next couple weeks.
ReplyDeleteHi Chris, I have already chosen a core - Zscale, I made that choice almost three weeks ago, almost immediately after I made this post. Just for a heads up - I have already completed porting the entire Vscale core modules to myhdl and the only part remaining is to assemble the modules and test the core :)
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