If you recall Bugs Bunny from the title, you are awesome :).
On a more serious note, This is officially the last post of this myhdl-riscv gsoc series :(.
I implemented a RISC-V based processor Zscale in myHDL and validated-verified it with unit and assembly tests.
As of today, the entire core (Zscale processor) is functional except for the assembly test of the core. My co-gsocer, +Srivatsan Ramesh and I are working on it and hopefully should get it done soon. My college started on July 19 which slowed down the last few weeks which majorly involved testing the core.
A more holistic review :
On a more serious note, This is officially the last post of this myhdl-riscv gsoc series :(.
I implemented a RISC-V based processor Zscale in myHDL and validated-verified it with unit and assembly tests.
As of today, the entire core (Zscale processor) is functional except for the assembly test of the core. My co-gsocer, +Srivatsan Ramesh and I are working on it and hopefully should get it done soon. My college started on July 19 which slowed down the last few weeks which majorly involved testing the core.
A more holistic review :
Original Work Plan
My main motivation in the project was to demonstrate the power and flexibility of myHDL by developing a RISC-V based core in myHDL. A few main checpoints in mind were :
Work Completed
* Pure Python Decoder (y)
* myHDL based Decoder(y)
* Vscale individual modules (y)
* Vscale assembly modules (y)
* Vscale unit tests (y)
* Vscale assembly tests (n)
* myHDL based Decoder(y)
* Vscale individual modules (y)
* Vscale assembly modules (y)
* Vscale unit tests (y)
* Vscale assembly tests (n)
Work Remaining
Links to commits
My Fork (more updated as I have a pending PR):
https://github.com/meetshah1995/riscv/commits/dev?author=meetshah1995
Main Repo (Contains all merged code ~5 PRs):
https://github.com/jck/riscv/commits/master?author=meetshah1995
Pull request(s) :
Pure Python RISC-V ISA Decoder Implementation
https://github.com/jck/riscv/pull/1
myHDL based RISCV 32I Decoder Implementation
https://github.com/jck/riscv/pull/2
Decoder module conversion and tests
https://github.com/jck/riscv/pull/3
Individual Vscale modules in myHDL
https://github.com/jck/riscv/pull/4
Assembly and test framework of Vscale in myHDL
https://github.com/jck/riscv/pull/5
Having said that, it gives me immense pleasure to have helped the myHDL & PSF community and would be more than glad if myHDL users used the riscv repository for their research and development.
It has been a great 3 months with a lot of learning and interaction experiences I gained on the way. Shout out to my mentors +Keerthan JC and +Christopher Felton for guiding my way through this seemingly difficult task.
I will promote myHDL in my university and contribute to the main myhdl repository in the coming months as and when I gather time.
Until next time,
MS.
My Fork (more updated as I have a pending PR):
https://github.com/meetshah1995/riscv/commits/dev?author=meetshah1995
Main Repo (Contains all merged code ~5 PRs):
https://github.com/jck/riscv/commits/master?author=meetshah1995
Pull request(s) :
Pure Python RISC-V ISA Decoder Implementation
https://github.com/jck/riscv/pull/1
myHDL based RISCV 32I Decoder Implementation
https://github.com/jck/riscv/pull/2
Decoder module conversion and tests
https://github.com/jck/riscv/pull/3
Individual Vscale modules in myHDL
https://github.com/jck/riscv/pull/4
Assembly and test framework of Vscale in myHDL
https://github.com/jck/riscv/pull/5
Having said that, it gives me immense pleasure to have helped the myHDL & PSF community and would be more than glad if myHDL users used the riscv repository for their research and development.
It has been a great 3 months with a lot of learning and interaction experiences I gained on the way. Shout out to my mentors +Keerthan JC and +Christopher Felton for guiding my way through this seemingly difficult task.
I will promote myHDL in my university and contribute to the main myhdl repository in the coming months as and when I gather time.
Until next time,
MS.
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