Verify -> Validate -> Vscale

As you probably can guess from the post title, the last few weeks was mostly about verifying and validating the vscale modules.

I developed unit tests for each module and now the ongoing work is to create unified tests for the entire assembly of modules. With the successful (*fingers crossed*) implementation of these tests, and some awesome documentation,  riscv module will finally come alive to be fully used by the myHDL community :) .


See you next week,
MS.