As the title may suggest , most part of the next part pf my GSoC will be making hardware modules for RISC-V cores and interfacing them to make a processor !.
I already have a working and tested myHDL based decoder in place. I am now in discussions with my mentor to finalize a RISC-V module which I can port to myHDL. This will embark the next phase of my coding in GSoC.
We will be selecting a RV32I based core to implement in the coming weeks as the HDL decoder fully supports RV32I at the present.
I have also shifted my development on the `dev` branch keeping my `master` up to date with the main repository.
See you next week.
MS
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